The Red Pitaya is essentially a two channel fast ADC and DAC connected to a Zynq series FPGA+SoC. The most common model (for which the applications described here are designed) is the STEMlab 125-14, which has 60MHz bandwidth and 14 bit resolution for both input and output.
To utilize the full capabilities of the hardware, it is helpful to make specialized FPGA designs. Presented here are designs I have created that I hope may be useful to others. My designs generally use minimal Vivado TCL scripts to generate connections to the processor and Verilog for functional modules (for details on how to setup and build these projects, see the setup and build instructions). I target the Red Pitaya 2.00 OS release; these projects will not be compatible with earlier versions (in particular, due to how the FPGA image is loaded).
These projects generally consist of a hardware design for the FPGA and a nearly SCPI compatible server that runs on the processor to provide user friendly remote access to the hardware design.
The significant deviation from SCPI compatibility is for binary arrays. For this server, these are encoded as binary with values 0 (\0), 10 (\n), and 92 (\) escaped with backslashes (\). This allows for relatively efficient transmission of arrays without special cases in the server or client (which can continue to assume results occupy a single line).
Red Pitaya Scope AWG
The Red Pitaya Scope AWG design is basic project that accesses CPU RAM from the FPGA. FPGA RAM is limited to <40kB, which limits the length of a signal that can be processed on the FPGA. Even a small 1MB portion of the CPU RAM allows much longer signals to be manipulated. This project implements an oscilloscope and a simple arbitrary waveform generator (not yet available via the server). This design is also intended to test setup and installation procedures, and thus has a number of static registers on the FPGA that are accessible via the server.
| SCPI Variables | |||
|---|---|---|---|
| Name | Data type | Read only | Description |
| :LEDs:4 | bool | False | Sets LED 4 |
| :LEDs:5 | bool | False | Sets LED 5 |
| :LEDs:6 | bool | False | Sets LED 6 |
| :LEDs:7 | bool | False | Sets LED 7 |
| :DEADbeef | uint | True | Returns 0xDEADBEEF |
| :ABADcafe | uint | True | Returns 0xABADCAFE |
| :BEEFbeef | uint | True | Returns 0xBEEFBEEF |
| :LOOP:INput | int | False | Sets the value of the loop |
| :LOOP:OUTput | int | True | Reads the value of the loop |
| :SCOPe:A | int16 binary array | True | Scope channel A trace |
| :SCOPe:B | int16 binary array | True | Scope channel B trace |
| :SCOPe:TRIGger | bool | False | Wait for trigger to start scope |
| :SCOPe:LENgth | uint | False | Length of scope trace |
| :SCOPe:STATus | uint | True | Scope status register |
| :SCOPe:CONTrol | enum | False | Write STARt to start scope, STOP to stop scope, RESET to reset scope, or WAIT to wait for recording to complete. ? returns current scope status. |
| :AWG:A | int16 binary array | False | AWG channel A trace |
| :AWG:B | int16 binary array | False | AWG channel B trace |
| :AWG:TRIGger | bool | False | Wait for trigger to start AWG |
| :AWG:LENgth | int | False | Length of AWG trace |
| :AWG:STATus | uint | True | AWG status register |
| :AWG:CONTrol | enum | False | Write STARt to start AWG, STOP to stop AWG, RESET to reset AWG, or WAIT to wait for output to complete. ? returns current AWG status. |
Red Pitaya Vector Network Analyzer
The Red Pitaya Vector Network Analyzer (RPVNA) uses the two DAC channels of the Red Pitaya to produce two sin waves (I and Q) of the same frequency with a 90° (tunable) phase shift between them while measuring the amplitude and phase of the signals at each input at that frequency. The frequency can then be swept. This allows the RPVNA to function as a swept sin vector network analyzer. While the swept sin approach has a slower cycle time than FFT based vector network analyzers, each frequency can be sampled for longer without storing the entire trace. This allows the RPVNA to reach narrow resolution bandwidths.
| SCPI Variables | |||
|---|---|---|---|
| Name | Data type | Read only | Description |
| :VNA:CONTrol | enum | False | STARt to start VNA, STOP to stop VNA, RESET to reset VNA, or WAIT to wait for recording to complete. ? returns currect VNA status. |
| :VNA:STARtfreq | float | False | Frequency to begin sweep at (Hz) |
| :VNA:STEPfreq | float | False | Frequency step size (Hz) |
| :VNA:LENgth | uint | False | Number of steps |
| :VNA:TIME | float | False | Time per step (s) |
| :VNA:AMPlitude | float | False | Amplitude (V), -1V to 1V |
| :VNA:QPHAseoffset | float | False | Phase offset for the Q output (output 2) (degrees). This must be set to +/-90 for amplitude and phase measurements to be reasonable. |
| :VNA:STATus | uint | True | VNA status register |
| :VNA:A:I | int32 binary array | True | Raw sum of product of input 1 with I sin wave |
| :VNA:A:Q | int32 binary array | True | Raw sum of product of input 1 with Q sin wave |
| :VNA:A:AMPlitude | float32 binary array | True | Amplitude of input 1 at each sweep frequency, computed as sqrt(I^2 + Q^2) |
| :VNA:A:PHAse | float32 binary array | True | Phase of input 1 at each sweep frequency, computed as arctan2(I, Q) |
| :VNA:B:I | int32 binary array | True | Raw sum of product of input 2 with I sin wave |
| :VNA:B:Q | int32 binary array | True | Raw sum of product of input 2 with Q sin wave |
| :VNA:B:AMPlitude | float32 binary array | True | Amplitude of input 2 at each sweep frequency, computed as sqrt(I^2 + Q^2) |
| :VNA:B:PHAse | float32 binary array | True | Phase of input 2 at each sweep frequency, computed as arctan2(I, Q) |
Red Pitaya Amplitude Lockbox
The Red Pitaya Amplitude Lockbox is a PI lockbox optimized for with integrator conditioning for anti-windup and conditioned transfer. Input 1 is used for process variable measurement. Input 2 can be used for an external setpoint. Output 1 is used for the control variable. The scope module from the Red Pitaya Scope AWG design is incorporated to provide a method to monitor the performance of the PI loop.
| SCPI Variables | |||
|---|---|---|---|
| Name | Data type | Read only | Description |
| :PID:SETpoint | float | False | Setpoint of the PI loop, when setpoint is not set to external (V) |
| :PID:SETpoint:EXTernal | bool | False | True to use input 2 for setpoint, false to use :PID:SETpoint for setpoint |
| :PID:P | float | False | P Coefficient (a.u.) |
| :PID:I | float | False | I Coefficient (a.u.) |
| :PID:MONitor:INput | float | True | Current input value (V) |
| :PID:MONitor:Error | float | True | Current error value (V) |
| :PID:MONitor:OUTput | float | True | Current output value (V) |
| :PID:MONitor:P | float | True | Current P*error result (a.u.) |
| :PID:MONitor:I | float | True | Current Integral(I*error) result (a.u.) |
| :PID:CONditioning:MINimum | float | False | Minimum obtainable control variable (V) |
| :PID:CONditioning:MAXimum | float | False | Maximum obtainable control variable (V) |
| :PID:CONditioning:SLOPe:MINimum | float | False | Minimum obtainable control variable derivative (V/s) |
| :PID:CONditioning:SLOPe:MINimum | float | False | Maximum obtainable control variable derivative (V/s) |
| :SCOPe:A | int16 binary array | True | Scope channel A trace |
| :SCOPe:B | int16 binary array | True | Scope channel B trace |
| :SCOPe:TRIGger | bool | False | Wait for trigger to start scope |
| :SCOPe:LENgth | uint | False | Length of scope trace |
| :SCOPe:STATus | uint | True | Scope status register |
| :SCOPe:CONTrol | enum | False | Write STARt to start scope, STOP to stop scope, RESET to reset scope, or WAIT to wait for recording to complete. ? returns currect scope status. |
Setup and Build
Setup Build Environment
Install a recent version of Vivado from Xilinx.com. "ML Edition" is suitable for these projects.
Building
Launch Vivado. In the TCL shell at the bottom, use cd to change to the hardware_design subdirectory of the cloned project. Then run source [project name].tcl. If there are no bugs, Vivado should begin building the project. The first time, the processor connections and other IP will be generated, causing Vivado to open (and then close) many windows. Subsequent runs will not regenerate these automatically (unless the hardware_design/bd subdirectory is deleted), and will thus be much faster. The FPGA bitsream will be stored in the hardware_design/out subdirectory.
To avoid issues with cross-compiling, the interfacing server is intended to be compiled on the Red Pitaya.
Installing
First, run ./upload.sh [Red Pitaya IP address] in a POSIX terminal (GNU/Linux, BSD, MacOS, or WSL). This script uses ssh and scp to copy the FPGA bitstream, server code, and helper scripts to the Red Pitaya in /root (the root user home directory). The uploaded files will be in a folder named red_pitaya_[abbreviated project name].
Next, open an ssh connection to the Red Pitaya. Use cd to change directory to the folder created by upload.sh. Build the server code by running make (this may take a few minutes). Install the FPGA bitstream by running ./rp_install.sh.
Running
First, open an ssh connection to the Red Pitaya. Use cd to change directory to the folder created by upload.sh. If the FPGA bitstream has been replaced, run ./rp_install.sh again. Start the server by running ./start.sh. If you wish to close the ssh connection, instead run nohup ./start.sh & to start the server in the background.
At this point, the system is ready to use. Open a raw socket connection to the SCPI server using the Red Pitaya IP address and port 5025. The non-standard command close should be used to cleanly disconnect from the SCPI server. The non-standard command shutdown can be used to stop the SCPI server. Note that the FPGA will continue running after the SCPI server is shutdown.